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[VHDL-FPGA-Verilog] USB_Interface

Description: verilog USB USB的slave fifo的控制-verilog USB
Platform: | Size: 2048 | Author: xuxf | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] FifoAndTestbench

Description: 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
Platform: | Size: 2048 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] Verilog_USB_OUT

Description: USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
Platform: | Size: 1153024 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] fifo_tb

Description: verilog implementation of 16X4 fifo with testbench
Platform: | Size: 1024 | Author: prateek | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] fifo_verilog

Description: 用verilog 实现 fifo，宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs
Platform: | Size: 4096 | Author: 张小琛 | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
Platform: | Size: 110592 | Author: 洪依 | Hits:

[Software Engineering] syn_fifo

Description: 基于systemverilog的异步fifo-fifo of design ，system verilog
Platform: | Size: 1024 | Author: weiwenqiang | Hits:

[VHDL-FPGA-Verilog] asy_fifo

Description: 用verilog实现异步fifo，通过仿真-Asynchronous with verilog fifo, the simulation
Platform: | Size: 1024 | Author: lily | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
Platform: | Size: 28672 | Author: benzema | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 此程序为verilog语言，实现的功能为FIFO功能，包括三个部分，分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Platform: | Size: 60416 | Author: liaoju | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用verilog实现FIFO，包含所有工程文件。-Verilog implementation using FIFO, includes all project files.
Platform: | Size: 1950720 | Author: 于志宏 | Hits:

[VHDL-FPGA-Verilog] FIFO-Design

Description: FIFO(first in first out)-first in first out, using verilog
Platform: | Size: 180224 | Author: 方舟 | Hits:

[VHDL-FPGA-Verilog] Fifo_lk

Description: 简单好用的Fifo 128x32 Verilog-Fifo 128x32 Verilog
Platform: | Size: 1024 | Author: liukang | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
Platform: | Size: 12288 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] Asynchronous-FIFO-Design

Description: 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
Platform: | Size: 3072 | Author: 林峰 | Hits:
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